The present invention relates in general to analog-to-digital converters, (ADCs) and, in particular, to methods and apparatuses for communicating high bit-rate data from an ADC to another device, such as a digital signal processor.
Analog-to-digital converters convert analog signals into digital signals, enabling the signal to be manipulated and processed using numerical techniques. ADCs are utilized, for example, to convert an analog audio signal into a digital form so that digital processing techniques may be utilized to provide features, such as volume control, frequency equalization, encryption, filtering, surround sound decoding, and ambiance effects. Additionally, digital signals are suitable for recording or transmitting to another location with no loss in signal quality.
Typically, an ADC converts an analog signal into digital words representing the amplitude of the audio signal at fixed intervals determined by the sampling rate or frequency. The data words are then transmitted to a digital signal processor (DSP), which manipulates the data words to provide various desired features. The ADC may transmit the digital words in a parallel format, e.g. eight or sixteen bits at a time; however, commodity DSPs often provide circuitry for receiving data serially, e.g., one bit at a time. Accordingly, integrated circuit ADCs often provide the digital data words in a compatible serial format.
In mixed signal integrated circuits, switching transients in the digital circuitry are known to create considerable noise and interference in the analog circuits. In an ADC, the noise may taint the accuracy or reduce the audible signal to noise ratio of the device. Because of the rapid switching involved, the actual transmission of data on the serial data (SDATA) line is a major source of noise and interference for sensitive analog circuitry within an ADC. One method to minimize such noise and interference, is to have the switching activity occur at specific times relative to noise sensitive operations. Previously, this has been accomplished by re-timing the operation of various circuits within the ADC as is described in U.S. Pat. No. 4,746,899, which is incorporated herein in its entirety. Retiming the serial transmission requires the master clock (MCLK) frequency be at least twice serial clock (SCLK).
In conventional stereo audio systems, a pair of audio channels are converted into digital form. Typically, a stereo ADC, having a pair of ADCs in a single integrated circuit package, is utilized to convert stereo audio into a digital form. A serial clock (SCLK) signal synchronizes the transmission and reception of each bit, and a channel clock (LRCK) signal differentiates between the left and right channels of data which are alternately transmitted. A master clock (MCLK) controls the internal operation of the ADC and DSP. Stereo audio uses a pair of audio channels, which provide a left channel and a right channel of audio; however, newer audio formats use more than two audio channels to provide a richer audio experience. For example, 5.1 channel audio, which is found on some DVD movie soundtracks, is utilized to create up to six channels of audio: a center front channel, left and right front channels, left and right surround channels, and a subwoofer channel. Digital audio formats capable of providing seven, eight, or more audio channels have also been developed.
For such high channel-count audio systems, the frequencies required to retime serial channel operation become more difficult, particularly at high sample rates. For example, an 8-channel system with 24-bit samples and a 192 kHz sample rate requires an SCLK frequency of about 36.8 MHz and a corresponding MCLK greater than about 73.7 MHz. Circuits using such high clock frequencies are difficult to design and use and, therefore, are not practical nor desirable. High bit rates also exacerbate the noise and interference problems in the analog portion of an ADC.
It would, therefore, be desirable to provide methods and apparatuses for serially transmitting digital audio signals with a high channel count and a high bit-rate without re-timing.
It would also be desirable to provide methods and apparatuses for serially transmitting digital audio signals with a high channel count and a high bit-rate while minimizing noise and interference.
It would also be desirable to provide methods and apparatuses for serially transmitting digital audio signals with a high channel count and a high bit-rate without the need for an excessively high master clock frequency.
Methods and apparatuses are provided for serially transmitting audio signals with a high-channel count and a high bit-rate without re-timing and without the need for an excessively high master clock frequency, while minimizing noise and interference.
A high bit-rate ADC with a serial interface for transmitting digital data words to another device is provided. In one embodiment, the ADC is a multi-channel ADC, and the serial interface uses a plurality of pins to serially transmit the digital data words. Each pin is utilized to transmit a different set of data channels so that multiple channels are concurrently transmitted. In a second embodiment of the multi-channel ADC, the serial interface is configured to transmit the data from all of the analog channels over a single serial data path, preferably using differential signaling. Multi-channel audio ADCs incorporating the principles of the present invention are able to transfer digital data at high bit rates without requiring excessive clock frequencies, while minimizing noise and interference to the analog circuitry.